The present application relates to semiconductor structures and methods of forming the same. More particularly, the present application relates to semiconductor structures containing a silicon germanium alloy fin that has reduced defects and extends upwards from a remaining portion of a silicon substrate and methods of forming the same.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, silicon fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Silicon fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In order to extend these devices for multiple technology nodes such as, for example, 10 nm and beyond, there is a need to boost the performance with high-mobility channels.
In such FinFET devices, a fin containing a silicon germanium alloy is one promising channel material because of its high-carrier mobility. Silicon germanium alloy fins can be formed by epitaxially growing a silicon germanium alloy layer on a surface of a silicon (Si) substrate and then patterning the silicon germanium alloy layer. This prior art method of forming silicon germanium alloy fins has some drawbacks associated therewith. For example, the direct epitaxial growth of a silicon germanium alloy on a Si substrate has a critical thickness limit. Above the critical thickness, silicon germanium is very defective and is not suitable for use as a device channel material. This prevents a thick silicon germanium alloy layer for high fin heights. Moreover, this approach is not scalable for silicon germanium alloy fins having a high (i.e., greater than 70 atomic %) germanium content.
Another approach is to provide silicon germanium alloy fins is to first form Si fins and shallow trench isolation (STI) structures and thereafter epitaxial grow a silicon germanium alloy fin on each sidewall surface of each Si fin. This approach overcomes the critical thickness problem mentioned above. However, silicon germanium alloy fins that are epitaxially grown on sidewall surfaces of a Si fin with the presence of dielectric oxide causes potential defect generation at the silicon germanium alloy fin/STI oxide corners.
In view of the above, there is a need for providing a method of forming silicon germanium alloy fins that avoids the drawbacks associated with prior art silicon germanium alloy fin formation.